Analog IC Explorer

About AICE

AICE is a symbolic circuit analysis program which is designed to help (not replace) analog IC designers do fast analysis work. If designers would like to acquire insight on a conceptual design, like transfer functions (TFs) of conceptual schematics, poles-zeros (PZs), effects of compensations, and effects of load, etc., AICE is a good helper. The key feature of AICE is to generate analytical results instantaneously for a given schematic, so fast that designers can almost use it to work out a target design by exploring different conceptual circuit topologies.

AICE can generate readable symbolic results. To use it, we recommend users to use it for analyzing conceptual (i.e., limited size) circuits rather than full-size transistor-level circuits. If the circuit scale is too large (involving too many parasitics), the generated results are going to be too complicated to read. We are developing another feature that can reduce a transistor-level circuit to a conceptual schematic before running TF and PZ analysis. But this development is not finished yet. We shall post a new tool with this feature as soon as it becomes available.

The symbolic analysis engine behind AICE is the GPDD (graph-pair decision diagram) algorithm originally proposed in [1]. A more thorough exposition on this algorithm is presented in the book [2]. The survey paper [3] provides more information on the BDD (binary decision diagram) technology and explains why this technology has revolutionary difference from other traditional symbolic analysis methods. In principle, this symbolic method can be applied to both large and small analog circuits. For large analog circuit the generated symbolic results would be too lengthy to read. However, on many occasions analog designers would like to view the symbolic results generated by a tool. In that case the schematic entered to the tool for analysis should not involve too many elements and connections. Most analog integrated circuits can be simplified and reduced to conceptual circuits by removing a great number of parasitics. AICE is a good tool for analyzing such conceptual circuits. A conceptual circuit is also a macromodel of a transistor-level circuit, which is commonly used for pole-zero analysis and compensation design.

GPDD is a symbolic analysis method that generates symbolic results by processing the circuit topology rather than an algebraic object like matrix. This is also the enabling technology inside AICE to generate reduced circuit automatically from a full-scale transistor-level circuit. We all this approach "topological circuit reduction"[4]. Topological circuit reduction is one type of symbolic model order reduction [6], but it requires that the reduced model remain to be a circuit. Because the reduced circuit preserves the frequency response behavior of the original circuit, the generated circuit is able to capture the structural configuration of the original transistor-level circuit. This is similar to what human designers often would do manually at the conceptual design stage.

A reduced circuit is compact with less number of circuit elements (which are used as the main design parameters). AICE can be used to generate simplified transfer functions and poles-zeros of such circuits. AICE employs the algorithm proposed in [5] to perform formal TF simplification so that the generated expressions are readable. Users can use the AICE-generated expressions for design exploration.

Summary of AICE functionalities

Already implemented

  • Schematic input
  • TF (transfer function) generation
  • PZ (pole-zero) generation (for multi-stage circuits)

To be implemented

  • Circuit reduction
  • Numerical calculation
  • Numerical plotting
  • Sizing support

AICE Developer

AICE is developed by the MSDA (Mixed-Signal Design Automation) Lab at Shanghai Jiao Tong University. Student currently in charge of the maintenance is Yu Hao If you have question or suggestions, please feel free to contact him. You are also welcome to write feedback by filling the message board online. This tool is the result of several evolutionary generations [7,8]. In [7] we reported the Qt version of the tool interface. The online AICE is redeveloped from [7] by rewriting the schematic interface and dialogs, and incorporating the pole-zero generation work [5]. The programming languages used for the AICE schematic input are JavaScript and HTML5. More technical details can be found in [8]. You are welcome to use AICE for personal learning, teaching, and research. If you consider publishing your work, please acknowledge this tool in the following format:

MSDA Lab., "AICE - Analog IC Explorer,", School of Microelectronics, Shanghai Jiao Tong University, 2017.

Thank you.


  1. Guoyong Shi, "Graph-Pair Decision Diagram Construction for Topological Symbolic Circuit Analysis," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 2, Feb. 2013, pp. 275-288.
  2. Guoyong Shi, Sheldon X.-D. Tan, E. Tlelo-Cuautle, Advanced Symbolic Analysis for VLSI Systems - Methods and Applications, Springer Science + Business Media, New York, 2014. (ISBN 978-1-4939-1102-8).
  3. Guoyong Shi, "A survey on binary decision diagram approaches to symbolic analysis of analog integrated circuits", Analog Integrated Circuits and Signal Processing, 74:331-343, 2013.
  4. Guoyong Shi, Hanbin Hu, and Shuwen Deng, "Topological approach to automatic symbolic macromodel generation for analog ICs," ACM Transactions on Design Automation of Electronic Systems, vol. 22, no. 3, 2017, pp. 47:1-25.
  5. Guoyong Shi, "Topological approach to symbolic pole-zero extraction incorporating design knowledge," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. xx, no. xx, 2017, appeared online.
  6. Guoyong Shi, B. Hu, and C.-J. R. Shi, "On symbolic model order reduction," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 7, pp. 1257-1272, July 2006. (Donald O. Pederson Best Paper Award 2007)
  7. Yanjie Gu and Guoyong Shi, "An interactive program for automatic network function generation with insights", International Symposium on Circuits and Systems (ISCAS), May, 2015, Lisbon, Portugal, pp. 1810-1813.
  8. Hao Yu and Guoyong Shi, “Developing a web-based symbolic circuit analysis tool for learning and design aid,” Proc. 14th Int’l Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), June 2017, Taormina, Italy.