Analog IC Explorer
AICE is a symbolic circuit analysis program which is designed to help analog IC designers do fast analysis work. If designers would like to acquire insight on a conceptual design, like transfer functions (TFs) of conceptual schematics, poles-zeros (PZs), effects of compensations, and effects of load, etc., AICE is a good helper. The key feature of AICE is to generate analytical results instantaneously given a schematic, so fast that designers can use it to work out a targeted design by exploring different conceptual circuit topologies.
AICE is designed to generate readable symbolic results. Hence, we recommend users to use it for analyzing conceptual circuits rather than full transistor-level circuits. If the circuit scale is too large (involving too many parasitics), the generated results are too complicated for reading. We are developing a feature that can reduce a transistor-level circuit to a conceptual schematic, but this development is not ready yet. We shall announce this feature as soon as it is ready online.
The symbolic analysis engine behind AICE is the GPDD (graph-pair decision diagram) algorithm originally proposed in . A more thorough exposition on this algorithm is presented in the book . The survey paper  provides more information on the BDD (binary decision diagram) technology and explains why this technology differs revolutionarily from the traditional symbolic analysis methods. In principle, this symbolic method can be applied to both large analog circuits and small analog circuits. For large analog circuit the generated symbolic results are too lengthy to be readable. However, on many occasions analog designers would like to view the symbolic results generated by a tool. In that case the schematic entered to the tool for analysis should not be too complicated. Most analog integrated circuits can be simplified and reduced to conceptual circuits by removing a great number of parasitics. The AICE tool is a good tool for analyzing such conceptual circuits. A conceptual circuit is also a macromodel of a transistor-level circuit. A conceptual circuit is also commonly used for pole-zero analysis and compensation design.
GPDD is a symbolic analysis method that generates symbolic results by processing the circuit topology rather than an algebraic object like matrix. This is also the enabling technology in AICE to generate reduced circuit automatically from a full-scale transistor-level circuit. This approach is called ``topological circuit reduction’’ . Topological circuit reduction is one type of symbolic model order reduction , but it requires that the reduced model remain to be a circuit. Because the reduced circuit preserves the frequency response behavior of the original circuit, the generated circuit is able to capture the structural configuration of the original transistor-level circuit. This is similar to what human designers often would do manually at the conceptual design stage. We are working on it to make this feature available online.
A reduced circuit is compact with less number of circuit elements (which are the main design parameters). The AICE tool can be used to generate simplified transfer functions and poles-zeros of such circuits. employs the algorithm proposed in  to perform formal TF simplification so that the generated expressions are readable. Users can use the AICE-generated expressions for design exploration.